Addressable boards in STDbus systems


Although the STDbus specification allows for as many as 32 address bits, many STDbus I/O slaves are designed to decode only eight or ten address bits. Such boards are said to be 8-bit addressable or 10-bit addressable, referenced to herein as "A-8" or "A-10", respectively. System integrators frequently ask: "How should A-8 and A-10 boards be configured for operation in my system?" This article attempts to answer that question, and to discuss important related topics as well.

The Problem

Fundamental to potential A-8/A-10 addressing problems is the notion of address aliasing. Address aliasing is defined as multiple instances of a physical device appearing in the system I/O map. Aliasing is the result when an I/O device does not decode all available address bits.

To get an idea of how aliasing works, consider how an A-8 board works within a 16-bit I/O address space. Suppose that the A-8 board is configured to decode at hexadecimal address B2, and the system software is designed to address the board at 00B2. Since the board ignores the upper address byte, the board will decode not only at 00B2, but also at 01B2, 02B2, ..., FFB2. In fact, the board will appear at any address XXB2, causing the board to appear at the desired address as well as at 255 address aliases in the I/O map.

From the above example, it is clear that address aliasing can potentially lead to addressing conflicts. A conflict will result if any alias is decoded by a different physical device.

The Solution

To completely resolve the address aliasing problem, it is necessary to eliminate all address aliases so that only one instance of each device appears in the system I/O map.

Fortunately, the STDbus includes a back plane signal — IOEXP — specifically intended to help eliminate address aliasing. The IOEXP signal is used as an address qualifier for I/O boards that decode fewer than 16 address lines. IOEXP is driven low during A-8/A-10 board accesses, and high at all other times. It is the responsibility of the STDbus Master (usually the CPU) to manage the IOEXP signal.

Unfortunately, not all STDbus CPU cards manage the IOEXP signal in quite the same way. Most newer CPUs designate a "window" — a range of addresses in the I/O map — for accessing A-8/A-10 boards. Some older CPUs don't provide any mechanism for managing IOEXP, particularly those CPUs designed before PC-compatible STDbus systems became popular.


Although STDbus CPU manufacturers have historically taken proprietary approaches to IOEXP signal management, some standards have recently emerged. A case in point is Ziatech's STD 32 Bus Specification.

Ziatech's approach is to define an address window from FC00-FFFF for accessing A-8 and A-10 boards. When the CPU accesses an I/O device within this window, IOEXP is driven low, thereby qualifying A-8/A-10 boards for decode. IOEXP is high at all other times, preventing A-8/A-10 boards from responding. All A-8/A-10 boards are configured to respond only when IOEXP is low, and all other I/O boards are configured to respond only when IOEXP is high.

Applying this approach to the earlier example, the A-8 board, which was mapped to address B2, would now appear at addresses FCB2, FDB2, FEB2 and FFB2. In this case, the system software might be designed to address the board at FCB2. Note that although three address aliases still exist (FDB2, FEB2 and FFB2), the aliasing problem is not as serious as before. More importantly, none of the aliases conflict with system devices, which generally reside below address 0400.

Getting Answers

At this point, you are armed with knowledge of the problem — address aliasing — and its general solution, but you may not have the information you need to effectively manage address aliasing in your specific application.

Begin by examining your CPU documentation. Nearly all manufacturers of modern STDbus CPUs have addressed this critical issue and documented their mechanism for interfacing A-8 and A-10 boards. Carefully review the I/O map and read any discussions relating to addressing A-8 and A-10 boards.

Occasionally, CPU documentation does not adequately describe the A-8 and A-10 board interface mechanism. In such a case, you must contact the CPU vendor. Since the CPU is responsible for addressing all memory and I/O devices in your system — including A-8 and A-10 boards — only the CPU manufacturer can advise you in this matter.

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